Miniaturization of semiconductor devices results in coping with soft error in latch circuits. Soft error is a phenomenon in which the logic of data retained in the latch circuit is inverted due to the influence of a rays emitted from a radioactive substance in a semiconductor device and neutron derived from cosmic rays. Recently, there has been proposed a semiconductor device in which the configuration of the latch circuit is duplicated as a measure for coping with the soft error. According to this proposal, in case where the logical inversion takes place at one node in the latch circuit due to soft error, data retained in the latch circuit is retained correctly.
Another phenomenon is known in which noise occurs in one of a plurality of transistors formed in an identical well, noise occurs in any of the others. This phenomenon is caused by a mechanism in which a decrease in the well potential of one of the transistors due to the function of charged particles results in decreases of the well potentials of other transistors close to the above one of the transistors, and is called parasitic bipolar effect. It is known that a soft error due to the parasitic bipolar effect occurs more frequently as the distance between a well contact for applying a predetermined voltage to the well and the transistor formed in this well is longer.
The inventors are aware of Japanese Laid-Open Patent Publication No. 2007-312104, and Oluwole A. Amusan, et al., “Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combination Logic”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, Vol. 54, No. 6, December 2007.
The duplicated latch circuit retains data correctly even when a logical inversion takes place at one node. However, if logical inversions occur simultaneously at two nodes due to the parasitic bipolar effect, the data retained in the latch circuit is inverted and data is destroyed.